An integrated memory, for instance, a DRAM (Dynamic Random Access Memory), generally has a memory cell array comprising word lines (rows) and bit lines (columns). The memory cells, respectively, are arranged at crossover points of the word lines and bit lines. The memory cells, which are usually used in integrated dynamic random access memories, generally have a memory cell capacitance and a selection transistor. The memory cell capacitances are, respectively, connected via the associated selection transistor of the respective memory cell to one of the bit lines via which a data signal is read out or written in. The control input of the selection transistor is connected to one of the word lines.
During a memory access, in particular, a write access, a word line is first activated. To this end, a command decoder previously receives an external access command for an access to the memory. An access controller for controlling the access to memory cells of the integrated memory is connected to the command decoder in order to receive internal command signals, which are output by the command decoder as a result of the external access command. The activation of a word line by the access controller causes the memory cells arranged along a word line to be respectively connected conductively to a bit line via the relevant selection transistor. In this case, the stored charge is divided in accordance with the memory cell capacitance and bit line capacitance. The bit line voltage is deflected in accordance with the ratio of these two capacitances. A read/write amplifier situated at one end of the bit line compares this voltage with the constant voltage on an associated complementary bit line and amplifies the relatively low potential difference between the bit line and the complementary bit line until the bit line has reached the full signal level for the corresponding data signal. At the same time, the inverse signal levels are reached on the associated complementary bit line.
After the memory cell array has been accessed, the previously selected word lines are deactivated. To this end, in the course of the memory access, the command decoder outputs a precharge command signal for precharging the corresponding word line, as a result of which the selected word line is brought into a precharging state. In this case, a delay time must be provided between the application and writing of the last data item and the application of the precharge command signal to the access controller, i.e., the write recovery time tWR, in order to be able to ensure that the data are written reliably within the memory cell array of the memory. Once the write recovery time has elapsed, the precharge command signal can be output to the access controller.
In-this case, it should generally be noted that, as the memory temperature falls, the writing window, which is specified by the write recovery time tWR, is increasingly situated in more critical areas in which it is only just possible to reliably write data. The reason for this is that, as the memory temperature falls, the time required to write data to the memory cell array increases on account of physical effects. If, in particular, in the case of SDRAMs (Synchronous Dynamic Random Access Memory), the operating frequency of the control clock is increased further in order to increase the throughput of data, the problem arises that, as the writing window tWR, e.g., a whole number of clock periods, becomes increasingly smaller as a result, it is no longer possible, under certain circumstances, in particular at lower temperatures, to reliably write data to the memory cell array. In this case, any limitations in the operational reliability of the memory when increasing the operating frequency would have to be accepted.